I'm an electrical engineer with a passion for electronics, signals, and systems. I received the B.S. degree in Electrical Engineering from the University of New Haven in 2017, and the M.S. degree in Electrical and Computer Engineering at Carnegie Mellon University in 2020. After my undergraduate degree, I worked as an electrical systems designer for large electrical power and control systems in New York City. I was part of an elite team of engineers conducting short circuit, coordination, and arc flash studies for mission critical clients, including banking data centers in the financial capital of the world.
While pursuing my masters degree, my renewed focus on analog circuits and data converters led to a concentration on mixed-signal integrated circuit design. As part of the Energy-Efficient Circuits and Systems Group, I worked on computational data converters and microelectronic circuits such as this Analog Neural Network. My research interests include low power data converters, RF and audio circuits, and brain-inspired machine learning circuits.
A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) converts an analog voltage to digital code by performing a binary search. Put simply, the ADC starts with a guess of the analog voltage value, then repeatedly refines this guess by comparing it to the true value. This project features SAR ADC designed by my team at Carnegie Mellon University and taped out in a 28-nm CMOS process in 2020. This 10-bit ADC targets more then 50 MSPS while operating with a 1mV LSB.
While the majority of ANNs exist in the digital domain, increasingly by semi-special purpose ICs like the GPU or TPU, the desire for always-on, low power edge computing has inspired some unique solutions that utilize analog or mixed-signal neural networks. In this project, I demonstrate how to build and train an artificial analog neural network that can compute common logic functions.
This paper describes the design of a low noise amplifier (LNA) employing a single-stage fully differential inductively degenerated cascode topology to achieve a low noise figure, high gain, high linearity, and good isolation between input and output nodes. An inband return loss (S11) of -13.2dB is obtained with a center frequency of 2.4GHz, while providing 25.8dB of voltage gain (S21) and a bandwidth of 300MHz. The amplifier consumes 5mW of power with a 1.2V supply, has a noise figure (NF) of 2.43dB, and an input referred third intercept point (IIP3) of -4.5dBm. The amplifier schematic has been realized in Cadence Virtuoso using a 65nm process, and the pre-layout performance has been simulated in SpectreRF.
